The present invention relates to an electrostatic-discharge (ESD) protecting circuit and method, and more particularly, to an electrostatic-discharge (ESD) protecting circuit and method in which ESD characteristic is improved to thereby prevent an internal circuit of a semiconductor device from being destroyed due to about 200-2,000 V of static electricity.
Generally, an ESD protecting circuit in a semiconductor device is designed to prevent an internal circuit from being destroyed by 200-2,000 V of static electricity. For this purpose, the ESD protecting circuit uses-a silicon controlled rectifier (SCR), or a field transistor, diode and bipolar transistor. However, due to increased integration of semiconductor devices, when a field transistor or bipolar transistor is used in the protecting circuit, a gate oxide layer to which high voltage is applied becomes so thin that the active devices included in the ESD protecting circuit, and in the internal circuit have ESD characteristics inferior to that of other active devices of the internal circuit. According to the prior art, the ESD characteristic is evaluated using the human body model (HBM) or the machine model (MM). In a currently manufactured semiconductor device, its internal circuit is formed using the same thickness of a gate oxide in one chip. For example, in case of 64M DRAM, a gate oxide layer having a thickness of about 100 .ANG. is used over the whole chip.
With higher integration of semiconductor devices, the package size is increased, and the gate oxide layer becomes thin. Accordingly, a technique which evaluates the ESD characteristic using the charged device model (CDM) has become powerful. The portion of the circuit destroyed by the HBM or MM method is the edges of a junction, while the portion destroyed by CDM method is mainly a gate oxide layer of the active devices. The time required for an ESD pulse applied by CDM method to reach maximum current is about 1 nsec, which is about the same time needed for the ESD protecting circuit to operate.
Accordingly, even before the operation of the ESD protecting circuit, the ESD pulse destroys the respective gate oxide layers of the active device included in the ESD protecting circuit, and of the active device connected to the internal circuit. Therefore, for higher integration of semiconductor devices, the ESD protecting circuit and the internal circuit around the protecting circuit as well as the active device connected to the ESD protecting circuit are affected by the electrostatic discharge.
FIG. 1 is a layout in which the active device is placed on a portion having a predetermined distance from the ESD protecting circuit, and FIG. 2 shows the change of the ESD voltage. Referring to FIGS. 1 and 2, it is known that the longer the distance is between the active device and the ESD protecting circuit, (for example, 50 .mu.m, 90 .mu.m, 120 .mu.m, or 150 .mu.m), the larger the ESD voltage that can be tolerated before failure occurs. That is, the ESD failure voltage of the active device placed apart from the ESD protecting circuit by about 150 .mu.m becomes about 1,500 V, but does not reach 2,000 V. This is because the excess charge, for example, hot carrier, caused by the ESD is not fully grounded, and affects adjacent active devices through the substrate, destroying the gate oxide layer or junction. Accordingly, the gate oxide layers of the active devices within the distance of about 200 to 300 .mu.m may be easily destroyed under the influence of the ESD.
Moreover, according to higher integration of semiconductor devices, a semiconductor device package is presently formed using a lead on chip (LOC) configuration suitable for increasing the packaging density. As shown in FIG. 1, the ESD protecting circuit in a LOC configuration is placed at the center, and the internal circuits are placed on both sides of the ESD protecting circuit. This increases the packaging density, but decreases the ESD breakdown voltage.
In addition, according to higher integration of semiconductor devices, the gate oxide layer becomes thinner such that the gate oxide layer of the active device constructing the internal circuit is damaged by the excess charge. Accordingly, as a method for preventing the gate oxide layer from being destroyed, it has been proposed to form a guard ring around the ESD protecting circuit to absorb the excess charge using the guard ring. This technique will be explained below with reference to the accompanying drawings.
FIG. 3 is a layout of an ESD protecting circuit of a conventional semiconductor device, and FIG. 4 is a cross-sectional view of a conventional ESD protecting circuit, taken along line IV--IV of FIG. 3. Referring to FIGS. 3 and 4, the conventional ESD protecting circuit 150 is formed between a signal input pad 100 of a high integration semiconductor device, and internal circuit 200. Signal input pad 100 is connected to the input terminal of internal circuit 200, and resistors R1 and R2 are connected between the signal input terminal 100 and input terminal of the internal circuit 200. Resistor R1 is a protection resistor, and is formed with a diffusion layer formed on the active region of a semiconductor substrate. Resistor R2 is a parasitic resistor, and is formed with a metal line formed on the semiconductor substrate. ESD protecting circuit 150 is formed between resistors R1 and R2, and includes parasitic bipolar transistors which will be explained below.
The conventional ESD protecting circuit is constructed in such a manner that a plurality of N+ type impurity regions 111, 112 and 113 are formed on a p-type semiconductor substrate 101 spaced apart from one another, and a heavily doped P+ type impurity region 115 is formed on p-type semiconductor substrate 101 around the N+ type impurity regions spaced therefrom. Here, N+ type impurity regions 111 and 113 are connected to a power supply terminal Vcc or ground Vss, and N+ type impurity region 112 is connected to the input pad 100. In this construction, N+ type impurity regions 111, 112 and 113 are connected to p-type semiconductor substrate 101, constructing a plurality of parasitic bipolar transistors 114. That is, N+ type impurity region 112 is used as a collector region of the parasitic bipolar transistor, and the N+ type impurity regions 111 and 113 are used as emitter regions thereof and P-type semiconductor substrate 101 acts as a base region thereof.
A gate oxide layer 209 and gate electrode 210 are formed on a portion of substrate 101 isolated from heavily doped P+ type impurity region 115. N+ type impurity regions 207 and 208 are formed on a portion of the substrate 101 on both sides of the gate electrode 210. The N+ type impurity regions 207 and 208, gate oxide layer 209 and gate electrode 210 form an MOS transistor 211 of the active device of the internal circuit.
In the conventional ESD protecting circuit described above, when the excess voltage caused by the ESD applied through input pad 100 is not emitted outside the device through the parasitic bipolar transistor 114, it is absorbed by the heavily doped P+ type impurity region 115. That is, when the excess voltage caused by the ESD is applied to the input pad 100, electrons which are not emitted through the parasitic bipolar transistor 114 are seized or trapped by holes in the P+ type impurity region 115, which is a heavily doped impurity region. By doing so, electrons are gradually discharged toward the p-type semiconductor substrate 101. Accordingly, active devices (for example, MOS transistor 211) of the internal circuit around P+ type impurity region 115 are prevented from being exposed to the excess voltage.
However, the conventional ESD protecting circuit has the following problems. First, when more than 2,000 V of excess voltage caused by the ESD due to CDM is applied through the pad, the excess voltage is applied to the active device of the internal circuit before the ESD protecting circuit begins operating. This may destroy the gate oxide layer of the active device, so that the internal circuit can not be protected from the ESD.
Secondly, the conventional ESD protecting circuit uses a polysilicon resistor, in order to make the ESD protecting circuit operate prior to the internal circuit by delaying the ESD pulse. This prevents the excess voltage from being applied to the internal circuit before the operation of the ESD protecting circuit. Accordingly, since the operating speed is reduced due to the addition of the resistor in the normal operation, the conventional ESD protecting circuit Is not suitable for high integration of semiconductor devices.